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SanDisk Industrial Grade CompactFlash 5000 Product Manual
© 2007 SanDisk® Corporation 38 July 2007
4.3 Memory Mapped Addressing
When CompactFlash Memory Card registers are accessed via memory
references, they appear in the common memory space window: 0-2K bytes as
shown in Table 33.
Table 33: Memory Mapped Decoding
-REG A10 A9A4 A3 A2 A1 A0 Offset -OE=0 -WE=0
1 0 X 0 0 0 0 0 Even RD Data a Even WR Data a
1 0 X 0 0 0 1 1 Error Register b Features b
1 0 X 0 0 1 0 2 Sector Count Sector Count
1 0 X 0 0 1 1 3 Sector No. Sector No.
1 0 X 0 1 0 0 4 Cylinder Low Cylinder Low
1 0 X 0 1 0 1 5 Cylinder High Cylinder High
1 0 X 0 1 1 0 6 Select
Card/Head
Select
Card/Head
1 0 X 0 1 1 1 7 Status Command
1 0 X 1 0 0 0 8 Dup Even RD
Data b
Dup Even WR
Data b
1 0 X 1 0 0 1 9 Dup Odd RD
Data b
Dup Odd WR
Data b
1 0 X 1 1 0 1 D Dup Error b Dup Features b
1 0 X 1 1 1 0 E Alt Status Device Ctl
1 0 X 1 1 1 1 F Drive Address Reserved
1 1 X X X X 0 8 Even RD Data c Even WR Data c
1 1 X X X X 1 9 Odd RD Data c Even RD Data c
a. Register 0 is accessed with -CE1 low and -CE2 low (and A0 = Do not care) as a
word register on the combined Odd Data Bus and Even Data Bus (D15-D0). This
register may also be accessed by a pair of byte accesses to the offset 0 with -CE1
low and -CE2 high. Note that the address space of this word register overlaps the
address space of the Error and Feature byte-wide registers that lie at offset 1.
When accessed twice as byte register with CE1 low, the first byte to be accessed
is the even byte of the word and the second byte accessed is the odd byte of the
equivalent word access. A byte access to register 0 with CE1 high and CE2 low
accesses the error (read) or feature (write) register.
b. Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at
offset 0 and 1.
Register 8 is equivalent to register 0, while register 9 accesses the odd byte.
Therefore, if the registers are byte accessed in the order 9 then 8 the data will be
transferred odd byte then even byte. Repeated byte accesses to register 8 or 0
will access consecutive (even then odd) bytes from the data buffer. Repeated
word accesses to register 8, 9 or 0 will access consecutive words from the data
buffer. Repeated byte accesses to register 9 are not supported. However,
repeated alternating byte accesses to registers 8 then 9 will access consecutive
(even then odd) bytes from the data buffer. Byte accesses to register 9 access
only the odd byte of the data.
c. Accesses to even addresses between 400h and 7FFh access register 8. Accesses
to odd addresses between 400h and 7FFh access register 9. This
1 KByte memory window to the data register is provided to enable hosts to
- SanDisk Industrial Grade 1
- CompactFlash 5000 1
- Table of Contents 2
- List of Tables 5
- Introduction 8
- Features 9
- CompactFlash Standard 10
- PCMCIA Standard 10
- Related Documentation 10
- Functional Description 10
- Technology Independence 11
- Defect and Error Management 11
- Bad Block Management 12
- Automatic Sleep Mode 12
- Power Supply Requirements 12
- Wear Leveling 12
- Product Specifications 14
- System Power Requirements 15
- System Performance 15
- System Reliability 16
- Physical Specifications 16
- Regulatory Compliance 17
- Traceability 17
- Interface Description 18
- Electrical Description 20
- Table 10: Signal Description 21
- Electrical Specification 24
- Output Drive Characteristics 25
- Power Up/Down Timing 26
- Common Memory Read Timing 27
- Table 16 (continued) 28
- Memory Timing Diagrams 29
- I/O Read Timing Diagram 30
- True IDE Mode 32
- Card Configuration 35
- Attribute Memory Function 36
- Attribute Memory function 37
- Attribute Memory) 38
- 202h in Attribute Memory) 39
- Memory) 40
- I/O Transfer Function 41
- Configurations 43
- Memory Mapped Addressing 45
- True IDE Mode Addressing 46
- ATA Registers 46
- Read Only) 47
- Device Control Register 50
- Offset Fh) 50
- ATA Command Description 52
- Check Power Mode–98H, E5H 53
- Erase Sector(s)–C0H 54
- Format Track–50H 55
- Identify Device–ECH 55
- Idle–97H, E3H 63
- Idle Immediate–95H, E1H 63
- Read Buffer–E4H 64
- Read DMA Command–C8H, C9H 64
- Read Multiple–C4H 65
- Read Long Sector–22H, 23H 66
- Read Sector(s)–20H, 21H 66
- Recalibrate–1XH 67
- Request Sense–03H 67
- Seek–7XH 68
- Set Features–EFH 69
- Set Multiple Mode–C6H 70
- Set Sleep Mode–99H, E6H 70
- Standby–96H, E2H 71
- Standby Immediate–94H, E0H 71
- Translate Sector–87H 72
- Wear Level–F5H 72
- Write Buffer–E8H 73
- Write DMA Command–CAH, CBH 73
- Write Long Sector–32H, 33H 73
- Write Multiple Command–C5H 74
- Write Sector(s)–30H, 31H 75
- Write Verify Sector(s)–3CH 76
- Error Posting 77
- CIS Description 78
- I. Warranty Statement 95
- II. General Provisions 95
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